Most digital integrated circuits require a clock signal to synchronize their activity. Often, a circuit will be designed so that the clock signal can come from more than one source. For example, it may either be generated internally on the chip, or be supplied externally. The motivation for such a design is flexibility and reduced power consumption: in some applications, there could already be an externally generated clock available and so to generate another clock on-chip is wasteful of energy. In other applications, no such external clock may be available. Since it is extremely expensive to produce many different variants of an integrated circuit, common practice is to design a chip to meet both requirements.
For this to be possible, there must exist a circuit for changing the source of the digital clock. Such a change-over must be glitch free, i.e. it must be possible to guarantee that the clock seen by the digital system neither has very short pulses, nor very closely spaced clock pulses. Since the internal and external clocks are asynchronous to one another, this change-over needs to be performed with some care. Typically, it is ensured that the first clock signal is paused for a sufficient duration, before the second clock signal is allowed to take over.
A conventional circuit for performing this function is shown in FIG. 1. The circuit 50 consists of two finite state machines (FSMs) 521, 522 that are responsible for managing the switch-over. Each FSM 521, 522 is associated with a clock input, Clk_A or Clk_B. The FSMs 521, 522 change their state on the 1->0 transition of the relevant clock input. Each FSM 521; 522 has an output ClkEn which, when set to 1, causes the respective clock to be passed to the clock output Clk_Out. The input signal Select, assumed to be synchronous to Clk_Out, specifies which clock should be active. Each FSM 521; 522 monitors the state of the other clock enable signal via the input OtherClkEn. Since the input clocks are assumed to be asynchronous to one another, it is necessary to use a double latch synchronizer 541, 542 for the input signals which come from other clock domains.
The circuit 50 disclosed in FIG. 1 also comprises two second double latch synchronizers 561, 562 connected to the FSMs 521, 522 and having the signal (Select) as inputs. The circuit 50 also comprises two AND-gates 581, 582 connected to the FSMs 521, 522 and to the clock sources Clk_A, Clk_B. As is apparent from FIG. 1, the AND-gates. 581, 582 are also connected to an OR gate 60 which has an output in the form of the clock output, Clk_Out.
The function of the circuit 50 is best explained via the state diagram for the FSMs 521, 522, shown in FIG. 2. The FSMs 521, 522 differ only in their reset behavior and the polarity of the Select signal to which they respond. It is assumed that Clk_A is to be enabled at reset, and Select is zero. The variable A in the state diagram is set to ‘1’ for the FSM 521 associated with Clk_A and set to ‘0’ for the FSM 522 associated with Clk_B.
At reset, both FSMs 521, 522 begin in the RESET state. The upper FSM 521 (A==1) proceeds into the ON state, asserts ClkEn and allows Clk_A to pass to Clk_Out. The lower FSM 522 (A==0) proceeds into the OFF state.
At some point, the system desires to change its clock source and changes Select to ‘1’. The upper FSM 521 observes the change, and proceeds to disable its clock by de-asserting ClkEn. Since the two FSMs 521, 522 are not synchronized, it is necessary for the lower FSM 522 to ensure that the upper FSM 521 has released the clock output. Therefore, on observing the change in Select, the lower FSM 522 proceeds to the WAIT state. Only when it observes that the upper FSM 521 has released the clock output (OtherClkEn==0) does it proceed to the ON state and allows the clock to pass.
The problem with the standard clock switch circuit 50 occurs when the clock to be switched to (for instance, Clk_B) is not present. This could be due to a misunderstanding about the application circuit, or due to a fabrication error of the integrated circuit. When the system requests to change the clock source, the upper FSM 521 will disable the output clock. However, the lower FSM 522 has no clock, and will never transition to the ON state. This causes a deadlock, since the system clock will not be restarted and so Select can not be changed. Such a deadlock is highly undesirable, as it means that the chip simply ceases to function with no diagnostic information and with no possibility to resume function in the alternative operating mode (using Clk_A).